New Post: "RISC-V Bytes: Timer Interrupts"

This post goes deep into how timer interrupts are enabled on @risc_v platforms and explores how a single machine mode timer can be used to expose one or more virtual timers to lower privilege levels.
danielmangum.com/posts/risc-v-

fun fact: you don't actually have to enable interrupts in machine mode to trigger timer interrupts from supervisor mode. As long as `mie.MTIE` is enabled, the fact that interrupts in higher privilege levels are always enabled when executing at a lower privilege level will cause a machine mode timer interrupt when `mtime` exceeds `mtimecmp`.

“And with as we finish dessert, I want everyone to move to the living room, where we will be introducing our new yearly family tradition… The Rotating of the Passwords!”

when you ask a vulnerability researcher to go sledding on Christmas.

Starting a learn section in the `moss` docs, beginning with a short list of terms and their definitions. Feel free to add more!
github.com/mosscomp/moss/pull/

Got the sequence I was looking for working now:
1. Machine mode timer interrupt (0x8...7) triggered by `mtime` exceeding `mtimecmp`.
2. Raise a supervisor timer interrupt (0x8...5) from the machine mode trap handler.
3. Handle in the supervisor trap handler because supervisor timer interrupts were delegated by setting the 5th bit in `mideleg`.

got the machine timer interrupts (exception code: 7) working in QEMU today.

it is Friday, December 23rd, and I am explaining HSTS to a friend over dinner.

When debugging timer interrupts on RISC-V it can be very helpful to set the memory-mapped `mtime` and `mtimecmp` registers to display on every step. When the latter exceeds the former a timer interrupt will become pending.

Quite honored that my RISC-V Bytes series is included in @WillFlux’s “Recommended FPGA Sites” alongside a bunch of folks I have tremendous respect for. Check out the list for some holiday reading!
projectf.io/recommended-fpga-s

Have you discovered any great #FPGA sites this year?

For #FPGAFriday this week, I’m sharing my favourites: projectf.io/recommended-fpga-s

lzop: “If you want the fastest compression and do not care about size, use level 1. If you want both worse compression time and larger size, use level 3.”
Source: stephane.lesimple.fr/blog/lzop

reply in comments with rationale for any of the choices as well!

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if you are running a mastodon server, who is your infrastructure provider?

who is going to make a laptop with a welled keyboard and take all of my money?

unclear how I ever used a keyboard that used staggered columns.

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