New Post: "RISC-V Bytes: Timer Interrupts"
This post goes deep into how timer interrupts are enabled on @risc_v platforms and explores how a single machine mode timer can be used to expose one or more virtual timers to lower privilege levels.
fun fact: you don't actually have to enable interrupts in machine mode to trigger timer interrupts from supervisor mode. As long as `mie.MTIE` is enabled, the fact that interrupts in higher privilege levels are always enabled when executing at a lower privilege level will cause a machine mode timer interrupt when `mtime` exceeds `mtimecmp`.
Starting a learn section in the `moss` docs, beginning with a short list of terms and their definitions. Feel free to add more!
Got the sequence I was looking for working now:
1. Machine mode timer interrupt (0x8...7) triggered by `mtime` exceeding `mtimecmp`.
2. Raise a supervisor timer interrupt (0x8...5) from the machine mode trap handler.
3. Handle in the supervisor trap handler because supervisor timer interrupts were delegated by setting the 5th bit in `mideleg`.
lzop: “If you want the fastest compression and do not care about size, use level 1. If you want both worse compression time and larger size, use level 3.”
reply in comments with rationale for any of the choices as well!